Audio Control FOUR.1i Specifications Page 14

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T0146-03
WCLK_x
BCLK_x
DOUT_x
DIN_x
t (DO-BCLK)
d
t (WS)
d
t (WS)
d
t (DI)
S
t (DI)
h
TLV320AIC34
SLAS538A OCTOBER 2007 REVISED NOVEMBER 2007
All specifications at 25 ° C, DVDD = 1.8 V
IOVDD = 1.1 V IOVDD = 3.3 V
PARAMETER UNIT
MIN MAX MIN MAX
t
d
(WS) ADWS/WCLK_x delay time 50 15 ns
t
d
(DO-BCLK) BCLK_x to DOUT_x delay time 50 15 ns
t
s
(DI) DIN_x setup time 10 6 ns
t
h
(DI) DIN_x hold time 10 6 ns
t
r
Rise time 30 10 ns
t
f
Fall time 30 10 ns
NOTE: All timing specifications are measured at characterization but not tested at final test.
Figure 2. DSP Timing in Master Mode
14 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC34
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