TERMINAL ASSIGNMENTS
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ZASPackage
(TopView)
P0061-01
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Table 1. TERMINAL FUNCTIONS, ALPHABETIC
TERMINAL
I/O DESCRIPTION
NAME BGA BALL
ADDR_A L7 I I
2
C address control A
ADDR_B L8 I I
2
C address control B
AVDD_DAC B3 – Analog DAC voltage supply, 2.7 V – 3.6 V
AVSS_ADC D8 – Analog ADC ground supply, 0 V
D4, E4, F4,
AVSS_DAC – Analog DAC ground supply, 0 V
G4
BCLK_A K3 I/O Audio serial data bus bit clock (input/output) A
BCLK_B L2 I/O Audio serial data bus bit clock (input/output) B
DIN_A K5 I Audio serial data bus data input (input) A
DIN_B L4 I Audio serial data bus data input (input) B
DOUT_A K6 O Audio serial data bus data output (output) A
DOUT_B L5 O Audio serial data bus data output (output) B
DRVDD B4, A4 – ADC analog and output driver voltage supply, 2.7 V – 3.6 V
DRVDD B9, A9 – Analog ADC and output driver voltage supply, 2.7 V – 3.6 V
DRVSS D5, D6, D7 – Analog output driver ground supply, 0 V
DVDD K1 – Digital core voltage supply, 1.65 V – 1.95 V
E8, F8, G8,
DVSS H4, H5, H6, – Digital core / I/O ground supply, 0 V
H8
GPIO1_A J2 I/O General-purpose input/output #1 – A
GPIO1_B J1 I/O General-purpose input/output #1 – B
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
GPIO2_A H2 I/O
input / audio serial data bus bit clock input/output – A
General-purpose input/output #2 (input/output) / digital microphone data input / PLL clock
GPIO2_B H1 I/O
input / audio serial data bus bit clock input/output – B
HPLCOM_A B7 O High-power output driver (left minus or multifunctional) A, capable of driving 8- Ω load
HPLCOM_B A7 O High-power output driver (left minus or multifunctional) B
HPLOUT_A B8 O High-power output driver (left plus) A, capable of driving 8- Ω load
HPLOUT_B A8 O High-power output driver (left plus) B
HPRCOM_A B6 O High-power output driver (right minus or multifunctional) A, capable of driving 8- Ω load
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