TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
The data busses of the TLV320AIC34 can be configured for left- or right-justified, I
2
S, DSP, or TDM modes of
operation, where communication with standard telephony PCM interfaces is supported within the TDM mode.
These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word
clock (WCLK_x or GPIO1_x) and bit clock (BCLK_x or GPIO2_x) can be independently configured in either
master or slave mode for flexible connectivity to a wide variety of processors.
The word clock (WCLK_x or GPIO1_x) is used to define the beginning of a frame, and may be programmed as
either a pulse or a square-wave signal. The frequency of this clock corresponds to the maximum of the selected
ADC and DAC sampling frequencies.
The bit clock (BCLK_x or GPIO2_x) is used to clock in and out the digital audio data across the serial bus. When
in master mode, this signal can be programmed in two further modes, continuous transfer mode and 256-clock
mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are
generated, so in general, the number of bit clocks per frame is two times the data width. For example, if data
width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is
used by a PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used.
These cases result in a low-jitter bit clock signal being generated, having frequencies of 32 × f
S
or 64 × f
S
. In the
cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal
period, due to the device not having a clean 40 × f
S
or 48 × f
S
clock signal readily available. The average
frequency of the bit clock signal is still accurate in these cases (being 40 × f
S
or 48 × f
S
), but the resulting clock
signal has higher jitter than in the 16-bit and 32-bit cases.
In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen.
The TLV320AIC34 further includes programmability to put the DOUT_x line in the high-impedance state during
all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit
clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in
multiple codecs able to use a single audio serial data bus.
The TLV320AIC34 also provides additional capability for ADCs and DACs within each partition (A or B) to run at
different data rates, which is described in more detail later in this datasheet. In this mode, both ADC and DAC
data are clocked using the same bit clock (BCLK_x) signal, but two word clock (WCLK_x) signals are used, one
for the ADC data and one for the DAC data. When configured for this mode of operation, the WCLK_x terminal is
used for the DAC word clock, while GPIO1_x can be used for the ADC word clock.
When the audio serial data busses are powered down while configured in master mode, the terminals associated
with the interfaces are put into a high-impedance state.
26 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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