Audio Control FOUR.1i Specifications download pdf (Page 31)

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(K R) / P´

PLL_CLKIN

CODEC

CODEC_CLKIN

PLL_OUT

MCLK_x BCLK_x

PLL_IN

B0153-02

DAC f

ADC f

CODEC_CLK=256 f´

S(ref)

CLKDIV_OUT

1/8

PLLDIV_OUT

CLKDIV_CLKIN

K=J.D

J=1,2,3,....,62,63

D=0000,0001,....,9998,9999

R=1,2,3,4,....,15,16

P =1,2,....,7,8

WCLK= /NCODEC

CODEC =DAC = ADC

SetNCODEC=NADC=NDAC=1,1.5,2,....,5.5,6

DACDRA =>NDAC=0.5

ADCDRA =>NADC=0.5

f f f

S(ref)

S S S

2/ Q

Q=2,3,….., 16,17

CLKDIV_IN

CLKDIV_CLKIN

2/(N M)´

CLKOUT_IN

CLKMUX_OUT

M=1,2,4,8

N=2,3,...,16,17

GPIO1_x

GPIO2_x

CLKOUT

TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

Figure 25. Audio Clock Generation Processing

The part can accept an MCLK_x input from 512 kHz to 50 MHz, which can then be passed through either a

programmable divider or a PLL, to get the proper internal audio master clock needed by the part. The BCLK_x or

GPIO2_x inputs can also be used to generate the internal audio master clock.

This design also allows the PLL to be used for an entirely separate purpose in a system, if the audio codec is not

powered up. The user can supply a separate clock to GPIO2_x, route this through the PLL, with the resulting

output clock driven out GPIO1_x, for use by other devices in the system.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK_x frequencies

available in the system. This device includes a highly programmable PLL to accommodate such situations easily.

The integrated PLL can generate audio clocks from a wide variety of possible MCLK_x inputs, with particular

focus paid to the standard MCLK_x rates already widely used.

When the PLL is disabled,

S(ref)

= CLKDIV_IN / (128 × Q)

Where Q = 2, 3, … , 17

CLKDIV_IN can be MCLK_x, BCLK_x, or GPIO2_x, selected by page 0, register 102, bits D7 – D6.

Product Folder Link(s): TLV320AIC34

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Audio Control FOUR.1i Specifications Page 31

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