TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 41: DAC Output Switching Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 Left-DAC Output Switching Control
00: Left-DAC output selects DAC_L1 path.
01: Left-DAC output selects DAC_L3 path to left line output driver.
10: Left-DAC output selects DAC_L2 path to left high-power output drivers.
11: Reserved. Do not write this sequence to these register bits.
D5 – D4 R/W 00 Right-DAC Output Switching Control
00: Right-DAC output selects DAC_R1 path.
01: Right-DAC output selects DAC_R3 path to right line output driver.
10: Right-DAC output selects DAC_R2 path to right high-power output drivers.
11: Reserved. Do not write this sequence to these register bits.
D3 – D2 R/W 00 Reserved. Write only zeros to these bits.
D1 – D0 R/W 00 DAC Digital Volume Control Functionality
00: Left- and right-DAC channels have independent volume controls.
01: Left-DAC volume follows the right-channel control register.
10: Right-DAC volume follows the left-channel control register.
11: Left- and right-DAC channels have independent volume controls (same as 00).
Page 0 / Register 42: Output Driver Pop Reduction Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D4 R/W 0000 Output Driver Power-On Delay Control
0000: Driver power-on time = 0 µ s
0001: Driver power-on time = 10 µ s
0010: Driver power-on time = 100 µ s
0011: Driver power-on time = 1 ms
0100: Driver power-on time = 10 ms
0101: Driver power-on time = 50 ms
0110: Driver power-on time = 100 ms
0111: Driver power-on time = 200 ms
1000: Driver power-on time = 400 ms
1001: Driver power-on time = 800 ms
1010: Driver power-on time = 2 s
1011: Driver power-on time = 4 s
1100 – 1111: Reserved. Do not write these sequences to these register bits.
D3 – D2 R/W 00 Driver Ramp-Up Step Timing Control
00: Driver ramp-up step time = 0 ms
01: Driver ramp-up step time = 1 ms
10: Driver ramp-up step time = 2 ms
11: Driver ramp-up step time = 4 ms
D1 R/W 0 Weak Output Common-Mode Voltage Control
0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply.
1: Weakly driven output common-mode voltage is generated from band-gap reference.
D0 R/W 0 Reserved. Write only zero to this register bit.
Page 0 / Register 43: Left-DAC Digital Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 1 Left-DAC Digital Mute
0: The left-DAC channel is not muted.
1: The left-DAC channel is muted.
D6 – D0 R/W 000 0000 Left-DAC Digital Volume Control Setting
000 0000: Gain = 0 dB
000 0001: Gain = – 0.5 dB
000 0010: Gain = – 1 dB
…
111 1101: Gain = – 62.5 dB
111 1110: Gain = – 63 dB
111 1111: Gain = – 63.5 dB
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 69
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