AUDIO DATA CONVERTERS
AUDIO CLOCK GENERATION
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
The TLV320AIC34 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. As described earlier, the A and B partitions
of the device can operate at entirely asynchronous sampling rates at the same time. The operation of a single
partition is described in detail as follows, although the description applies equally to both partitions.
The data converters are based on the concept of an f
S(ref)
rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f
S(ref)
is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to provide different sampling rates on the ADC and
DAC simultaneously, and also to enable high-quality playback of low-sampling-rate data without high-frequency
audible noise being generated.
The sampling rate of the DAC can be set to f
S(ref)
/NDAC or 2 × f
S(ref)
/NDAC, with NDAC being 1, 1.5, 2, 2.5, 3,
3.5, 4, 4.5, 5, 5.5, or 6.
While only one f
S(ref)
can be used at a time in one partition, the ADC and DAC sampling rates can differ from
each other by using different NADC and NDAC divider ratios for each. For example, with f
S(ref)
= 44.1 kHz, the
DAC sampling rate can be set to 44.1 kHz by using NDAC = 1, while the ADC sampling rate can be set to
8.018 kHz by using NADC = 5.5.
When the ADCs and DACs are operating at different sampling rates, an additional word clock is required, to
provide information regarding where data begins for the ADC versus the DAC. In this case, the standard bit clock
signal (which can be supplied through the BCLK_x terminal or through GPIO2_x) is used to transfer both ADC
and DAC data, the standard word clock signal is used to identify the start of the DAC data, and a separate ADC
word clock signal (denoted ADWK) is used. This clock can be supplied or generated from GPIO1_x at the same
time the DAC word clock is supplied or generated from WCLK_x.
The audio converters in the TLV320AIC34 need an internal audio master clock at a frequency of 256 × f
S(ref)
,
which can be obtained in a variety of manners from an external clock signal applied to the device.
A more detailed diagram of the audio clock section of the TLV320AIC34 is shown in Figure 25 .
30 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TLV320AIC34
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