ToDetectionblock
HPLOUT_x
HPLCOM_x
HPROUT_x
HPRCOM_x
MICDET_x
Thisswitchcloseswhen
jackisremoved
B0245-01
CONTROL REGISTERS
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
An output configuration for the case of the outputs driving fully differential stereo headphones is shown in
Figure 38 . In this mode, there is a requirement on the jack side that either HPLCOM_x or HPLOUT_x be shorted
to ground if the plug is removed. This requirement can be implemented using a spring terminal in a jack. For this
mode to function properly, short-circuit detection should be enabled and configured to power down the drivers if a
short circuit is detected. The register that controls this functionality is in page 0, register 38, bits D2 – D1.
Figure 38. Configuration of Device for Jack Detection Using
a Fully Differential Stereo Headphone Output Connection
The control registers for the TLV320AIC34 are mapped into page 0 and page 1. Page 0 is used to configure the
codec analog and digital pathways, whereas page 1 is used to program digital filter coefficients. The
TLV320AIC34 is a four-channel codec that contains a partition of two stereo codecs, codec A and codec B.
Because all of the functionality of each partition is identical, page 0 and page 1 are only shown once in the
following register descriptions. Note that only page 0, register 101 for codec block A is different than page 0,
register 101 for codec block B, so page 0, register 101 is shown twice in the following register listing. Each of
these status registers displays the I
2
C register address based on the respective state of the ADDR_A and
ADDR_B terminals.
Because the two stereo codecs in the TLV320AIC34 are independent, none of the register values are shared.
Therefore, BOTH codecs, codec A and codec B, must be completely and independently programmed — codec A
using its unique I
2
C address, and also codec B using its unique I
2
C address. All I
2
C registers are 8 bits in width,
with D7 referring to the most-significant bit of each register, and D0 referring to the least-significant bit.
Page 0 / Register 0: Page Select Register
READ/ RESET
BIT
(1)
DESCRIPTION
WRITE VALUE
D7 – D1 X 0000 000 Reserved. Write only zeros to these register bits.
D0 R/W 0 Page Select Bit
Writing zero to this bit sets page 0 as the active page for subsequent register accesses. Writing a one to
this bit sets page 1 as the active page for subsequent register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes.
(1) When resetting registers related to routing and volume controls of output drivers, it is recommended to reset them by writing directly to
the registers instead of using software reset.
52 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
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