Audio Control FOUR.1i Specifications download pdf (Page 28)

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S MODE

BCLK_x

WCLK_x

1 1

0 0

T0151-03

1/fs

LSBMSB

LeftChannel

RightChannel

2 2

DIN_x/

DOUT_x

n n n

1ClockBeforeMSB

n–1 n–1n–2 n–2

DSP MODE

BCLK_x

WCLK_x

0 0

1 0 n nn

T0152-02

1/fs

LSB LSBLSB MSB MSB MSB

LeftChannel

RightChannel

1 12 2

DIN_x/

DOUT_x

n–1 n–1n–1n–2 n–2 n–2

TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

In I

S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge

of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after

the rising edge of the word clock.

Figure 22. I

S Serial Data Bus Mode Operation

In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and

immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 23. DSP Serial Bus Mode Operation

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Audio Control FOUR.1i Specifications Page 28

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