TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 46: PGA_LP_x and PGA_LM_x to HPLOUT_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to HPLOUT_x.
1: PGA_LP_x and PGA_LM_x is routed to HPLOUT_x.
D6 – D0 R/W 000 0000 PGA_LP_x and PGA_LM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 47: DAC_L1 to HPLOUT_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT_x.
1: DAC_L1 is routed to HPLOUT_x.
D6 – D0 R/W 000 0000 DAC_L1 to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 48: LINE2RP_x and LINE2RM_x to HPLOUT_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2RP_x and LINE2RM_x Output Routing Control
0: LINE2RP_x and LINE2RM_x is not routed to HPLOUT_x.
1: LINE2RP_x and LINE2RM_x is routed to HPLOUT_x.
D6 – D0 R/W 000 0000 LINE2RP_x and LINE2RM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 49: PGA_RP_x and PGA_RM_x to HPLOUT_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_RP_x and PGA_RM_x Output Routing Control
0: PGA_RP_x and PGA_RM_x is not routed to HPLOUT_x.
1: PGA_RP_x and PGA_RM_x is routed to HPLOUT_x.
D6 – D0 R/W 000 0000 PGA_RP_x and PGA_RM_x to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 50: DAC_R1 to HPLOUT_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLOUT_x.
1: DAC_R1 is routed to HPLOUT_x.
D6 – D0 R/W 000 0000 DAC_R1 to HPLOUT_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
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