Audio Control FOUR.1i Specifications download pdf (Page 32)

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TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

NOTE – when NDAC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK_x can be

as high as 50 MHz, and f

S(ref)

should fall within 39 kHz to 53 kHz.

When the PLL is enabled,

S(ref)

= (PLLCLK_IN × K × R) / (2048 × P), where

P = 1, 2, 3, … , 8

R = 1, 2, … , 16

K = J.D

J = 1, 2, 3, … , 63

D = 0000, 0001, 0002, 0003, … , 9998, 9999

PLLCLK_IN can be MCLK_x or BCLK_x, selected by page 0, register 102, bits D5 – D4.

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal

point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of

precision).

Examples:

If K = 8.5, then J = 8, D = 5000

If K = 7.12, then J = 7, D = 1200

If K = 14.03, then J = 14, D = 0300

If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified

performance:

2 MHz ≤ (PLLCLK_IN / P) ≤ 20 MHz

80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz

4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified

performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz

80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz

4 ≤ J ≤ 11

R = 1

Example:

MCLK = 12 MHz and f

S(ref)

= 44.1 kHz

Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f

S(ref)

= 48 kHz

Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

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Audio Control FOUR.1i Specifications Page 32

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