TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 86: LEFT_LOP_x and LEFT_LOM_x Output Level Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D4 R/W 0000 LEFT_LOP_x and LEFT_LOM_x Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010 – 1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 LEFT_LOP_x and LEFT_LOM_x Mute
0: LEFT_LOP_x and LEFT_LOM_x is muted.
1: LEFT_LOP_x and LEFT_LOM_x is not muted.
D2 R 0 Reserved. Do not write to this register bit.
D1 R 1 LEFT_LOP_x and LEFT_LOM_x Volume Control Status
0: All programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied.
1: Not all programmed gains to LEFT_LOP_x and LEFT_LOM_x have been applied yet.
D0 R 0 LEFT_LOP_x and LEFT_LOM_x Power Status
0: LEFT_LOP_x and LEFT_LOM_x is not fully powered up.
1: LEFT_LOP_x and LEFT_LOM_x is fully powered up.
Page 0 / Register 87: LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2LP_x and LINE2LM_x Output Routing Control
0: LINE2LP_x and LINE2LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: LINE2LP_x and LINE2LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
D6 – D0 R/W 000 0000 LINE2LP_x and LINE2LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 88: PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Volume Control
Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 PGA_LP_x and PGA_LM_x Output Routing Control
0: PGA_LP_x and PGA_LM_x is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: PGA_LP_x and PGA_LM_x is routed to RIGHT_LOP_x and RIGHT_LOM_x.
D6 – D0 R/W 000 0000 PGA_LP_x and PGA_LM_x to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Page 0 / Register 89: DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Volume Control Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP_x and RIGHT_LOM_x.
1: DAC_L1 is routed to RIGHT_LOP_x and RIGHT_LOM_x.
D6 – D0 R/W 000 0000 DAC_L1 to RIGHT_LOP_x and RIGHT_LOM_x Analog Volume Control
For 7-bit register setting versus analog gain values, see Table 7 .
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 81
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