Audio Control FOUR.1i Specifications download pdf (Page 53)

www.ti.com

TLV320AIC34

SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007

Page 0 / Register 1: Software Reset Register

READ/ RESET

BIT DESCRIPTION

WRITE VALUE

D7 W 0 Software Reset Bit

0 : Don ’ t care

1 : Self-clearing software reset

D6 – D0 W 000 0000 Reserved. Do not write to these bits.

Page 0 / Register 2: Codec Sample Rate Select Register

READ/ RESET

BIT DESCRIPTION

WRITE VALUE

D7 – D4 R/W 0000 ADC Sample Rate Select

0000: ADC f

= f

S(ref)

0001: ADC f

= f

S(ref)

/1.5

0010: ADC f

= f

S(ref)

0011: ADC f

= f

S(ref)

/2.5

0100: ADC f

= f

S(ref)

0101: ADC f

= f

S(ref)

/3.5

0110: ADC f

= f

S(ref)

0111: ADC f

= f

S(ref)

/4.5

1000: ADC f

= f

S(ref)

1001: ADC f

= f

S(ref)

/5.5

1010: ADC f

= f

S(ref)

1011 – 1111: Reserved. Do not write these sequences to these register bits.

D3 – D0 R/W 0000 DAC Sample Rate Select

0000 : DAC f

= f

S(ref)

0001 : DAC f

= f

S(ref)

/1.5

0010 : DAC f

= f

S(ref)

0011 : DAC f

= f

S(ref)

/2.5

0100 : DAC f

= f

S(ref)

0101 : DAC f

= f

S(ref)

/3.5

0110 : DAC f

= f

S(ref)

0111 : DAC f

= f

S(ref)

/4.5

1000 : DAC f

= f

S(ref)

1001: DAC f

= f

S(ref)

/5.5

1010: DAC f

= f

S(ref)

/ 6

1011 – 1111 : Reserved. Do not write these sequences to these register bits.

Page 0 / Register 3: PLL Programming Register A

READ/ RESET

BIT DESCRIPTION

WRITE VALUE

D7 R/W 0 PLL Control Bit

0: PLL is disabled.

1: PLL is enabled.

D6 – D3 R/W 0010 PLL Q Value

0000: Q = 16

0001: Q = 17

0010: Q = 2

0011: Q = 3

0100: Q = 4

…

1110: Q = 14

1111: Q = 15

D2 – D0 R/W 000 PLL P Value

000: P = 8

001: P = 1

010: P = 2

011: P = 3

100: P = 4

101: P = 5

110: P = 6

111: P = 7

Product Folder Link(s): TLV320AIC34

1 2 ... 48 49 50 51 52 53 54 55 56 57 58 ... 97 98

Comments to this Manuals

No comments

Audio Control FOUR.1i Specifications Page 53

Comments to this Manuals

Related products and manuals for Car media receivers Audio Control FOUR.1i