TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
Page 0 / Register 108: Passive Analog Signal Bypass Selection During Power Down Register
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 LINE2RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
D6 R/W 0 LINE2RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
D5 R/W 0 LINE1RM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM_x.
D4 R/W 0 LINE1RP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP_x.
D3 R/W 0 LINE2LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
D2 R/W 0 LINE2LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
D1 R/W 0 LINE1LM_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM_x.
D0 R/W 0 LINE1LP_x Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP_x.
(1) Based on the settings of this register, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches
used for the connection short the two input signals together on the output terminals. The shorting resistance between the two input
terminals is two times the bypass switch resistance (Rdson). In general, this condition of shorting should be avoided, as higher drive
currents are likely to occur on the circuitry that feeds these two input terminals of this device.
Page 0 / Register 109: DAC Dynamic Range Selection Register
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D6 R/W 00 DAC Dynamic Range Adjustment
00: Default (Dynamic range specified in electrical characteristics table)
01: Dynamic range enhancement level 1
10: Reserved
11: Dynamic range enhancement level 2
D5 – D0 R/W 00 0000 Reserved. Write only zeros to these register bits.
Page 0 / Register 110 – 127: Reserved Registers
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 – D0 R 0000 0000 Reserved. Do not write to these registers.
Page 1 / Register 0: Page Select Register
BIT READ/ RESET DESCRIPTION
WRITE VALUE
D7 – D1 X 0000 000 Reserved. Write only zeros to these register bits.
D0 R/W 0 Page Select Bit
Writing zero to this bit sets page 0 as the active page for subsequent register accesses. Writing a one to
this bit sets page 1 as the active page for subsequent register accesses. It is recommended that the user
read this register bit back after each write, to ensure that the proper page is being accessed for future
register read/writes. This register has the same functionality on page 0 and page 1.
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