Audio Control FOUR.1i Specifications Page 27

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RIGHT-JUSTIFIED MODE
BCLK_x
WCLK_x
1
00
1
0
T0149-03
1/fs
LSBMSB
LeftChannel
RightChannel
2 2
DIN_x/
DOUT_x
n nn–1 n–1n–2
n–2
LEFT-JUSTIFIED MODE
BCLK_x
WCLK_x
1 1
0 00
T0150-03
1/fs
LSBMSB
LeftChannel
RightChannel
2 2
DIN_x/
DOUT_x
n n nn–1 n–1 n–1n–2 n–2
TLV320AIC34
SLAS538A OCTOBER 2007 REVISED NOVEMBER 2007
In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling
edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding
the rising edge of the word clock.
Figure 20. Right-Justified Serial Bus Mode Operation
In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling
edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following
the rising edge of the word clock.
Figure 21. Left-Justified Serial Data Bus Mode Operation
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TLV320AIC34
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