I
2
C CONTROL MODE
SDA
SCL
t
HD-STA
0.9 s³ m
t
SU-STO
0.9 s³ m
P
S
t
SU-STA
0.9 s³ m
Sr
t
HD-STA
0.9 s³ m
S
T0114-02
TLV320AIC34
SLAS538A – OCTOBER 2007 – REVISED NOVEMBER 2007
The TLV320AIC34 supports the I
2
C control protocol using 7-bit addressing and capable of both standard and fast
modes. For I
2
C fast mode, note that the minimum timing for each of t
HD-STA
, t
SU-STA
, and t
SU-STO
is 0.9 µ s, as seen
in Figure 16 . The TLV320AIC34 uses two I
2
C addresses, with the A channels controlled through one device
address, and the B channels controlled using a different device address. These addresses can be modified
through use of the ADDR_A and ADDR_B terminals, as described in the following table.
ADDR_A = 1 ADDR_A = 0 ADDR_B = 1 ADDR_B = 0
A I
2
C address 001 1010 001 1000
B I
2
C address 001 1011 001 1001
Figure 16. I
2
C Fast-Mode Timing Requirements
This capability to modify the I
2
C addresses allows two TLV320AIC34 codecs to be used on a single I
2
C control
bus, providing individual control of each codec. This provides up to eight channels of audio codec controlled from
a single host processor I
2
C peripheral.
I
2
C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the
I
2
C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH.
Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving
them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver
contention.
Communication on the I
2
C bus always takes place between two devices, one acting as the master and the other
acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of
the master. Some I
2
C devices can act as masters or slaves, but the TLV320AIC34 can only act as a slave
device.
An I
2
C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted
across the I
2
C bus in groups of eight bits. To send a bit on the I
2
C bus, the SDA line is driven to the appropriate
level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA
line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver
shift register.
The I
2
C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads
from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. The
master always drives the clock line. The TLV320AIC34 never drives SCL, because it cannot act as a master. On
the TLV320AIC34, SCL is an input only when configured as an I
2
C terminal.
Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 23
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